1. Field of the Invention
The present invention relates to a process of integrated circuit packaging, and in particular to a method of positioning and affixing an integrated circuit component on a package substrate.
2. Description of the Prior Art
Interconnection and packaging related issues are among the main factors that determine not only the number of circuits that can be integrated on a chip, but also the performance of the chip. These issues have increased in importance as advances in chip design have led to reductions in the sizes of features on transistors and enlargements in chip dimensions. Industry has come to realize that merely having a fast chip will not result in a fast system; it must also be supported by equally fast and reliable packaging.
Essentially, packaging supplies the chip with signals and power, and performs other functions such as heat removal, physical support and protection from the environment. Another important function of the package is simply to redistribute the tightly packed inputs and outputs (I/Os) off the chip to the I/Os of a printed circuit wiring board.
An example of a package-chip system is the "flip-chip" integrated circuit mounted on an area array organic package. Flip-chip mounting entails placing solder bumps on a die or chip, flipping the chip over, aligning the chip with the contact pads on a package substrate, and reflowing the solder balls in a furnace to establish bonding between the chip and the substrate. This method is advantageous in certain applications because the contact pads are distributed over the entire chip surface rather than being confined to the periphery as in wire bonding and most tape-automated bonding (TAB) techniques. As a result, the maximum number of I/O and power/ground terminals available can be increased, and signal and power/ground interconnections can be more efficiently routed on the chips. With flip-chip packaging, proper alignment of the chip and the package is essential to ensure proper operation of the final assembly.
In prior art processes, solder balls, or bumps, are formed on metalized interconnect pads (gold pads) on a surface of an integrated circuit die. Each solder ball corresponds to a conjugate interconnect pad on the surface of a substrate, such as a package board. The integrated circuit die is then positioned on the substrate so that the solder balls lie on top of the substrate interconnect pads. The die and package are then placed together into a reflow oven where they are heated to the melting, or reflow, point of the solder balls. The solder balls melt, forming connections between the die and package interconnect pads.
The general methodology of flip-chip packaging may also be applied to packaging of multi-chip modules. A multi-chip module is essentially a package on which are affixed multiple chips, such as memory chips. In a flip-chip manufacturing process, a multi-chip module is connected to a package substrate, such as a printed circuit board, in a manner similar to that applied to a single die. The challenges and problems associated with multi-chip modules are similar to those encountered with dice.
Hereinafter, integrated circuit chips and dice, multi-chip modules, transistors and other similar integrated circuit devices are referred to in a generic sense as integrated circuit components. This class of components includes solid-state devices generally attached to a printed circuit board in the integrated circuit packaging arts.
It is often desirable when packaging an integrated circuit assembly that there be space between the integrated circuit component, such as a chip, die or multi-chip module, and the package substrate. The resulting space may be left empty, to facilitate heat exchange with the ambient environment, or the space may be filled with an underfill material to add strength to the integrated circuit package assembly, and electrical insulation to the integrated circuit component solder connections. However, providing for space between an integrated circuit component and a package substrate presents problems as discussed below.
It is known that if solder balls used in prior art processes are made of low-melting, or eutectic, solder, the solder balls will have a tendency to collapse under the weight of a multi-chip module during reflowing. In FIGS. 1A and 1B, side views of an integrated circuit package assembly 10, made by a prior art process, are depicted. FIG. 1A is a side view of an integrated circuit package assembly 10 according to a prior art process, prior to a reflowing step. Multi-chip module 12 has an upper surface 110, a lower surface 102, and a plurality of solder balls 104 disposed on contact pads (not shown) on the lower surface 102 of the multi-chip module 12. The multi-chip module 12 has been positioned on a surface 16 of a substrate 14 so that the solder balls 104 are precisely aligned with cognate substrate interconnect pads (not shown) on the substrate surface 16. A die 120, having an upper surface 122, is also positioned on the surface 16 of substrate 14. The upper surface 122 of die 120 and the upper surface 110 of multi-chip module 12 lie at initial z-height "a" above the substrate surface 16.
In FIG. 1B, the same integrated circuit package assembly 10 is shown after a reflowing step. During the reflowing step, solder balls 104 from FIG. 1A have collapsed to form solder connectors 106 between substrate 14 and multi-chip module 12. The solder connectors 106 assume a pancake-like shape. The upper surface 110 of multi-chip module 12 is now at final z-height b, which is lower than the upper surface 122 of die 120. In other words z-height b is less than z-height a. As mentioned above, this leads to one or more undesirable results. For instance, if it were desirable to underfill multi-chip module 12, it would be impractical to do so given the reduced clearance between substrate surface 16 and module lower surface 102. On the other hand, decreased space between substrate surface 16 and module lower surface 102 results in less efficient heat exchange between ambient air and the multi-chip module 12. Such decreased heat exchange efficiency generally results in higher incidence of thermal breakdown, shorter component life, and poor integrated circuit performance in general. Other problems that arise in similar situations is uneven collapse of solder balls 106, which results in differing lengths of solder balls 106. Where connectors are of different lengths, it can be anticipated that they will have different inductive reactance, different tolerances to mechanical stress, and a greater likelihood to break prematurely. Again, the result is an integrated circuit package that performs more poorly than is desirable.
In an effort to overcome the above-mentioned disadvantages in prior art methods of packaging integrated circuit components, some prior art processes use standoffs to maintain the z-height of integrated circuit components, such as chips, dice and multi-chip modules. Such standoffs are generally conductive pieces, such as metal pieces, which are placed on metalized contact pads, or gold pads, of a multi-chip module to maintain separation between multi-chip modules and the substrates during reflowing. Known standoffs are formed from electrically conductive metal, such as copper, that will not melt and will therefore maintain its shape during reflowing of solder balls.
FIGS. 2A and 2B depict a prior art integrated circuit package that uses standoffs. FIG. 2A is a side view of an integrated circuit package assembly 20, prior to a reflowing step. FIG. 2B is the same integrated package assembly 20 after a reflowing step.
In FIG. 2A, a multi-chip module 22 has an upper multi-chip module surface 202, a lower multi-chip module surface 204, and standoffs 212, which are disposed on contact pads (not shown) on the lower multi-chip module surface 204. On the end of each standoff 212 is a solder ball 214. A substrate 24 has a top surface 26, on which are disposed substrate interconnect pads (not shown). The solder balls 214 rest on top of cognate interconnect pads (not shown) on substrate top surface 26. A die 220, having an upper surface 222, is also located on substrate top surface 26. The upper surface 222 of die 220, and the upper surface 202 of multi-chip module 22, lie at an initial z-height c above the top surface 26.
When the integrated circuit package assembly 20 is subjected to reflowing in a reflowing furnace, the solder balls 214 melt and flow up the standoffs 212 by capillary action.
FIG. 2B shows the integrated circuit package assembly 20 after a reflowing step. Hourglass-shaped connectors 230 comprise solder 224 encasing standoffs 212 (dashed lines). The upper surface 202 of multi-chip module 12 is at final z-height d above top surface 26 of substrate 14. The upper surface 202 of multi-chip module 12 is substantially parallel to substrate top surface 26, although final z-height d is lower than z-height d of upper surface 222 of die 220.
Thus, certain prior art manufacturing methods have a disadvantage of requiring formation of metal standoffs on each of the metalized interconnect pads of a multi-chip module. Each standoff must have a solder ball placed on the end thereof. During the manufacturing process, especially in a step of positioning a multi-chip module on a substrate, solder balls are subjected to lateral stresses that tend to break the solder balls off of the standoffs. Moreover, formation of standoffs on each metalized interconnect pad of a multi-chip module is a complex procedure and adds additional steps to the packaging process. Also, care must be taken in choosing solder and standoff metal, because barrier potentials between solder and standoff metal may lead to spurious currents and voltages, and may further result in degradation of the connections through formation of metal oxide layers between the solder and standoff metal.
Prior art processes have a further disadvantage in that z-height of a multi-chip module will change during reflowing. As the solder balls melt, the standoffs sink through the melting solder, sometimes in an uneven fashion. The result is that the z-height of the multi-chip module may vary across its top surface. Additionally, one side of the multi-chip module may heat faster than another, resulting in different rates of melting of solder balls. In such cases, the multi-chip module may become so skewed from its desired conformation that some of the solder contacts may not span the gap between the multi-chip module and the package. All of these considerations add to the costs of manufacturing integrated circuit packages including multi-chip modules.
There is therefore a need in the art for a flip-chip manufacturing process that provides for constant z-height of an upper surface of multi-chip modules and other integrated circuit components, but that does not suffer from the complexities and increased costs associated with prior art processes involving the use of metal standoffs.
It is also known in the integrated circuit packaging art to use fiducial marks to check the orientation of a substrate so that components, such as dice and multi-chip modules, are placed in correct positions on package substrates, such as package boards. One such arrangement is shown in FIG. 3, which is a top view showing a substrate 30 having a substrate surface 32. The substrate surface 32 has an imaginary x-y coordinate system, which assists a camera recognition system (not shown) in visualizing the substrate surface 32. The camera recognition system is advantageously part of a Panasonic chip placement tool (not shown) having machine vision. On the substrate surface 32 is a die position 36 and a multi-chip module position 34. A plurality of substrate interconnect pads (not shown) are located on the substrate surface 32 within the die position 36. The position of each substrate interconnect pad corresponds to a die connector pad (not shown) on the surface of a die (not shown). It is imperative that the die be properly placed on the substrate surface 32 so that the substrate connector pads and the die connector pads (not shown) are precisely aligned.
The prior art substrate 30 of FIG. 3 uses four fiducial marks 302, 304, 306 and 308. The fiducial marks 302 are distributed about the surface 32 of package substrate 30 in such a way as to allow a chip placement tool (not shown) to properly position the package substrate 30 using a camera recognition system. Generally, fiducial marks 302, 304, 306 and 308 are distributed roughly symmetrically on the surface 32 of package substrate 30.
In the prior art, substrate 30 of FIG. 1 is positioned on a die placement tool (not shown) such as a Panasonic brand die placement tool with a camera recognition system (machine vision). The placement tool (not shown) uses machine vision to locate the fiducial marks 302, 304, 306 and 308. The die placement tool determines the location of the fiducial marks 302, 304, 306 and 308 using machine vision, and then uses the location of fiducial marks 302, 304, 306 and 308 to determine the orientation of the substrate 30 on the die placement tool. The die placement tool then uses this information as a guide in precisely positioning a die (not shown) on the substrate surface 32.
Prior art processes using fiducial marks (also called detects) as visualization marks for guiding die placement tools require screen printing of fiducial marks on the substrate surface 30. Screen printing is a subprocess that requires masking of the substrate surface 32 with an appropriate resist layer (not shown), applying gold colored marking material to the substrate surface 32, and then removing the resist layer. Fiducials often serve no purpose after bonding of integrated circuit components to package substrates. As they add no value to post-packaged integrated circuit assemblies, it is desirable to develop a process that permits visualization of the substrate surface 32 by an integrated circuit component placement tool without the need for screen printing of fiducial marks. Thus, prior art processes using fiducial marks have the disadvantage of requiring extra steps, manufacturing machinery and material, which in turn increase the cost, manufacturing complexity, error rate and time required for flip-chip manufacturing processes, without adding post-production value to the final product.
There is therefore a need in the art for a process of manufacturing an integrated circuit package assembly that permits a die placement tool to visualize the position of a package substrate, while avoiding, the additional steps of screen printing fiducial marks on substrate surfaces.